1. Field of the Invention
The present invention relates to a delay circuit for creating a delay in a square wave.
2. Description of the Related Art
A delay circuit for creating a delay in a square wave is used in a delay locked loop (DLL), for example. FIG. 7 is a block diagram showing the structure of a DLL. The DLL has a phase detector (PD) 2, a charge pump 4, a capacitor C, and a voltage controlled delay line (VCDL) 6.
A square-wave input signal Vin is input to the phase detector 2 and the voltage controlled delay line 6. The voltage controlled delay line 6 outputs to the phase detector 2 a delay signal Vd1 for creating the delay of Vin in a quantity that corresponds to a delay control signal Vcnt. The phase detector 2 produces a difference signal composed of a pulse whose width corresponds to the phase difference between Vin and Vd1, and outputs the pulse to the charge pump 4.
The charge pump 4 converts the difference signal from the phase detector 2 to an electric current, an electric current directed so that the capacitor C is charged is produced in a period in which the pulse in the difference signal is at an H (high) level, and an electric current directed so that the capacitor C is discharged is produced in a period in which the pulse is at an L (low) level. The capacitor C integrates the output current of the charge pump 4 and produces a voltage (error signal) that corresponds to the integration result. The error signal is supplied to the voltage controlled delay line 6 as the delay control signal Vcnt.
The voltage controlled delay line 6 includes a plurality of delay cells connected in series. FIG. 8 is a circuit diagram of a delay cell. The delay cell shown in FIG. 8 has a differential amplifier circuit in which transistors M01, M02 constitute a differential pair. The differential output of the preceding cell is input as an input signal Vcin to the differential pair. Transistors M03, M04 functioning as load resistors are connected to the transistors M01, M02, respectively. The transistors M03, M04 are used in a triode region, and the on-resistance Ron thereof is controlled by the delay control signal Vcnt impressed on a gate. The output signal Vcout of the differential amplifier circuit creates a delay relative to the input signal Vcin in accordance with the time constant τ (≡Ron·Ct) of an RC circuit composed of Ron and Ct, where Ct is the capacitance between the ground and the output terminal of the delay cell. In a case in which, for example, the transistors M03, M04 are p-channel MOS transistors, the delay time of the voltage controlled delay line 6 increases as a result of the fact that the on-resistance Ron and the value of τ both increase when the voltage Vcnt increases in the positive region.    Patent Document 1: JP-A 2008-136031